Bus Pirate Firmware Automated continuous builds

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Hardware Log Download Created Commit hash Build time  
NG1 SUCCESS 2019-05-26 14:47:58 fcc6acb 11.76s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-26 14:47:28 rename temporary variables 10 5 5 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 10 5 5
BPU ERROR! 2019-05-26 14:24:42 3ad6f1e 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-26 14:23:52 fix OUT FIFO shift and pop logic 46 26 20 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 21 12 9
hdl/buspirate/buspirate_tb.gtkw modified 25 14 11
BPU ERROR! 2019-05-26 13:30:14 7a42f88 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-26 13:29:42 Add read test. fix bug in synchronizer. 71 38 33 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate_tb.gtkw modified 41 26 15
hdl/buspirate/buspirate_tb.v modified 28 11 17
hdl/buspirate/synchronizer.v modified 2 1 1
BPU ERROR! 2019-05-26 12:35:46 b4a8538 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-26 12:35:33 cleanup old variables. fix == vs === assignments. add initial values. 53 29 24 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 21 10 11
hdl/buspirate/buspirate_tb.gtkw modified 27 14 13
hdl/buspirate/synchronizer.v modified 5 5 0
BPU ERROR! 2019-05-26 10:58:11 96aa3bc 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-26 10:57:42 read/write FIFO. in fifo seems to be 100% working. out fifo just has some bidirectional config issues. 50 25 25 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 50 25 25
BPU ERROR! 2019-05-26 10:18:05 68ba237 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-26 10:17:01 restore clock use and use sync'ed we input 6 4 2 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 6 4 2
BPU ERROR! 2019-05-26 10:13:56 48d8758 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-26 10:13:04 add synchronizer for external levels. Now we're cooking! 237 145 92 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 103 56 47
hdl/buspirate/buspirate_tb.gtkw modified 29 20 9
hdl/buspirate/buspirate_tb.v modified 87 51 36
hdl/buspirate/synchronizer.v added 18 18 0
BPU ERROR! 2019-05-25 11:01:32 10434fa 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-25 11:00:46 modify buffer phy module to do bidirectional 7 6 1 URL
Filename Status Changes Additions Deletions
hdl/buspirate/iobufphy.v modified 7 6 1
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-25 11:01:22 added output FIFO and attached to SPI 89 46 43 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 52 33 19
hdl/buspirate/buspirate_tb.gtkw modified 33 10 23
hdl/buspirate/buspirate_tb.v modified 4 3 1
BPU ERROR! 2019-05-25 08:19:08 41cf642 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-25 08:10:03 Merge branch 'master' of https://github.com/DangerousPrototypes/Bus_Pirate_Ultra 4721 2549 2172 URL
Filename Status Changes Additions Deletions
hardware/scratch/BusPirate-ng.v4.0.brd modified 2469 1426 1043
hardware/scratch/BusPirate-ng.v4.0.sch modified 2252 1123 1129
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-25 08:12:17 git ignore for all hdl 5 4 1 URL
Filename Status Changes Additions Deletions
hdl/.gitignore renamed 5 4 1
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-25 08:12:54 buspirate module fix move bytes from MC to FIFO to SPI! 13 10 3 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 13 10 3
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-25 08:13:24 clock divider, pwm, and spi modules from SMDprutser 531 531 0 URL
Filename Status Changes Additions Deletions
hdl/clkdivider/clkdivider.v added 53 53 0
hdl/clkdivider/clkdivider_tb.v added 44 44 0
hdl/pwm/pwm.v added 75 75 0
hdl/pwm/pwm_tb.v added 62 62 0
hdl/spi/buspirate.pcf added 83 83 0
hdl/spi/spi2.v added 119 119 0
hdl/spi/spi_tb.v added 95 95 0
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-25 08:19:00 frequency counter and state machine from SMDprutser 175 175 0 URL
Filename Status Changes Additions Deletions
hdl/bitstream-header.xls modified 0 0 0
hdl/freqcnt/freqcount.v added 67 67 0
hdl/freqcnt/freqcount_tb.v added 60 60 0
hdl/statemachine/bp.v added 48 48 0
BPU ERROR! 2019-05-24 16:55:19 2df2819 0.01s
Committer Date Message Changes Additions Deletions Diff
vimark 2019-05-24 16:54:20 renumber parts 3284 1642 1642 URL
Filename Status Changes Additions Deletions
hardware/scratch/BusPirate-ng.v4.0.brd modified 1120 560 560
hardware/scratch/BusPirate-ng.v4.0.sch modified 2164 1082 1082
BPU ERROR! 2019-05-24 16:36:45 20e0af3 0.01s
Committer Date Message Changes Additions Deletions Diff
vimark 2019-05-24 16:36:17 fix board labels 497 355 142 URL
Filename Status Changes Additions Deletions
hardware/scratch/BusPirate-ng.v4.0.brd modified 497 355 142
BPU ERROR! 2019-05-24 14:54:53 2a05c48 0.01s
Committer Date Message Changes Additions Deletions Diff
vimark 2019-05-24 14:54:36 connect remaining loose nets, finished routing -connect VCC of 74LVCT45 to pull-up voltage VPUN -connect pull-up resistors of FPGA_CRESET and FPGA_CDONE to to 3V3 1192 678 514 URL
Filename Status Changes Additions Deletions
hardware/scratch/BusPirate-ng.v4.0.brd modified 1078 624 454
hardware/scratch/BusPirate-ng.v4.0.sch modified 114 54 60
BPU ERROR! 2019-05-24 14:43:33 784d6da 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-24 14:42:37 simplified fifo, still several major issues 90 57 33 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 2 1 1
hdl/buspirate/buspirate_tb.gtkw modified 33 27 6
hdl/buspirate/buspirate_tb.v modified 16 11 5
hdl/buspirate/fifo.v modified 39 18 21
BPU ERROR! 2019-05-24 13:25:20 4d2cf1c 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-24 13:24:51 added fifo based on https://github.com/cliffordwolf/icotools/blob/master/icosoc/common/icosoc_crossclkfifo.v . needs work still... 116 111 5 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 26 22 4
hdl/buspirate/buspirate_tb.v modified 4 3 1
hdl/buspirate/fifo.v added 86 86 0
BPU ERROR! 2019-05-24 10:39:39 8b9e27c 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-24 10:39:26 spi master directly connected to 0x00 write address. all BPIO pins and buffers now connected and have been simulated. 275 246 29 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 52 46 6
hdl/buspirate/buspirate_tb.gtkw modified 39 23 16
hdl/buspirate/buspirate_tb.v modified 67 60 7
hdl/buspirate/spimaster.v added 117 117 0
BPU ERROR! 2019-05-23 17:37:52 20f66bd 0.01s
Committer Date Message Changes Additions Deletions Diff
vimark 2019-05-23 17:37:28 continue routing power traces 450 263 187 URL
Filename Status Changes Additions Deletions
hardware/scratch/BusPirate-ng.v4.0.brd modified 450 263 187
BPU ERROR! 2019-05-23 16:41:20 bf50e7b 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-23 16:29:32 simulation of memory controller interface. 0x19 writes to the PWM (50% duty fixed). had to make the data pins input only and remove the SB_IO instantiation, this needs further investigation. 59 46 13 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 19 14 5
hdl/buspirate/buspirate_tb.gtkw modified 14 10 4
hdl/buspirate/buspirate_tb.v modified 26 22 4
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-23 16:40:54 change address decoder to case statement 8 5 3 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 8 5 3
BPU ERROR! 2019-05-23 08:54:49 2dfb87f 0.01s
Committer Date Message Changes Additions Deletions Diff
vimark 2019-05-23 08:53:44 route power traces 563 356 207 URL
Filename Status Changes Additions Deletions
hardware/scratch/BusPirate-ng.v4.0.brd modified 563 356 207
BPU ERROR! 2019-05-22 09:57:51 a3ba018 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-22 09:57:05 add time scale (not accurate). add gtkw config file to show default signals and zoom to fit in simulation 27 27 0 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate_tb.gtkw added 26 26 0
hdl/buspirate/buspirate_tb.v modified 1 1 0
BPU ERROR! 2019-05-22 09:22:47 74d6547 0.01s
Committer Date Message Changes Additions Deletions Diff
ian 2019-05-22 09:21:57 fix comparison operator in verilog fake buffer for simulation 7 4 3 URL
Filename Status Changes Additions Deletions
hdl/buspirate/buspirate.v modified 2 1 1
hdl/buspirate/buspirate_tb.v modified 1 1 0
hdl/buspirate/iobufphy.v modified 4 2 2